Technological advances have permitted semiconductor integrated circuits to comprise significantly more circuit elements in a given silicon area. Reducing and eliminating defects in the circuit elements has, however, become increasingly more difficult with the increased number of circuit elements. To achieve higher population capacities, circuit designers strive to reduce the size of the individual circuit elements to maximize available die real estate. The reduced size makes these circuit elements increasingly susceptible to defects caused by material impurities during fabrication.
Nevertheless, defects are identifiable upon completion of the integrated circuit fabrication by testing procedures, either at the semiconductor chip level or after complete packaging. Scrapping or discarding defective integrated circuits when defects are identified is economically undesirable, particularly if only a small number of circuit elements are actually defective.
Relying on zero defects in the fabrication of integrated circuits is an unrealistic option. Therefore, redundant circuit elements are provided on integrated circuits to reduce the number of scrapped integrated circuits. If a primary circuit element is determined to be defective, a redundant circuit element is substituted for the defective primary circuit element. Substantial reductions in scrap arc achieved by using redundant circuit elements without substantially increasing the cost of the integrated circuit.
One type of integrated circuit device using redundant circuit elements is integrated memory circuits, such as dynamic random access memories (DRAMs), static random access memories (SRAMs), video random access memories (VRAMs), and erasable programmable read only memories (EPROMs). Typical integrated memory circuits comprise millions of equivalent memory cells arranged in arrays of addressable rows and columns. The rows and columns of a memory cell array are the primary circuit elements of the integrated memory circuit. By providing redundant circuit elements, either as rows or columns, defective primary rows or columns can be replaced with functional ones.
Decoders perform an essential task by selecting the functional rows and columns of the integrated memory array. The memory cells within an integrated memory array are coupled to an electronic system through the address and data lines. Decoder circuits interface between the address lines and the array of memory cells.
A conventional decoder circuit of a semiconductor memory device comprises one or more separate decoder units which supply decode output signals according to an input address signal. A row decoder selects the appropriate row and the column decoder selects the appropriate column corresponding to a particular memory cell within the memory array. The pair of decoder output signals are also referred to wordlines, which corresponds to a row decoder, and bitlines, which correspond to a column decoder.
Decoders contain the required logic functions required to properly address desired memory cells within a memory cell array. Traditionally, decoder circuits are masked with a logic configuration for selecting rows and columns. Once the logic function has been masked, it is very difficult to make a correction. An improperly programmed decoder results in an integrated memory device functioning incorrectly.
A technique used to correct a decoder after it has been masked is to use ion beams or lasers. Making corrections to a decoder after it has been programmed is a very time consuming and cumbersome process using these common techniques.
To provide some level of programmability in a decoder, antifuses are used. To program an antifuse "on," a large programming voltage is applied across the antifuse terminals, breaking down the interposed dielectric and forming a conductive link between the antifuse terminals. An unprogrammed "off" state, in which the antifuse is fabricated, presents a high resistance between the antifuse terminals. The antifuse can be reprogrammed to an "on" state in which a low resistance connection between the antifuse terminals is desired, but only for a very limited number of times.
Therefore, a problem with current row and column decoders is that once they are programmed with a particular logic function, changes are often difficult and complex to make. If a decoder is not properly programmed, the integrated memory circuit will likewise not function properly, which defeats the purpose of having redundant circuit elements on an integrated memory array. There are elaborate techniques to reprogram a decoder, but these techniques are cumbersome and time consuming. Therefore, there is a need in the art for a decoder that can be easily reprogrammed.
Another problem with decoders is that as integrated circuit technology advances, the size of individual circuit elements decreases. Designers can include more storage cells in a memory array on a semiconductor substrate. As the number of storage cells increases, the number of components in a decoder likewise need to increase.
Increasing the storage capacity of a decoder array requires a reduction in the size of the transistors and other components in order to increase the decoder's density. However, memory density is typically limited by a minimum lithographic feature size (F) imposed by lithographic processes used during fabrication. For example, the present generation of high density decoders require an area of 8F.sup.2 per bit of data. Therefore, there is a need in the art to provide even higher density decoders in order to further support the increased storage capacity of integrated memory circuits.